In the manufacture of semiconductor integrated circuits (ICs), deep and shallow isolation trenches are extensively used, in particular in the manufacture of 16 Mbits DRAM chips. Deep trenches are created in a silicon substrate to define the storage capacitors while shallow trenches are used to isolate each capacitor trench from its neighbours. As far as shallow isolation trenches are concerned, a conventional process includes three basic steps: (1) forming shallow trenches in a silicon substrate provided with a patterned Si.sub.3 N.sub.4 layer (IT mask), (2) filling said trenches with a layer of an insulating material such as TEOS SiO.sub.2 and (3) planarizing the insulating layer. All these processing steps are conducted in the Shallow Trench Isolation (STI) module. The planarization basic step mentioned above is basically comprised of two main steps: (1) forming a layer of a planarizing medium having a substantially planar surface onto the TEOS SiO.sub.2 layer and (2) a RIE etching (AB etch) followed by a chemical-mechanical polishing of the structure (referred to hereinbelow as the planarization main step). The aim of the planarization basic step as a whole is to produce a surface of the TEOS SiO.sub.2 as planar as possible without any defect.
FIG. 1 schematically illustrates a structure 10 which is a part of a wafer consisting of a silicon substrate 11 with a passivation layer 12 formed thereon. Typically, this passivation layer 12 consists of a 14.5 nm thick SiO.sub.2 bottom layer and a 175 nm (nominal) thick top Si.sub.3 N.sub.4 layer. The passivation layer 12 will be referred to hereafter as the Si.sub.3 N.sub.4 layer 12 for sake of simplicity. Basically, substrate 11 is comprised of two regions 13 and 14 referred to as the "array" and ".kerf/support/street" regions respectively. The memory elements, each being comprised of an active device (an IGFET) and a capacitor are integrated in the "array" area. The ".kerf/support/street" area includes all the test devices and the "glue" circuitry that are necessary to make these memory elements operative. Deep isolation trenches are only formed in the "array" region 13 as standard. Two deep trenches referenced 15A and 15B are shown in FIG. 1. Each deep trench, generically referenced 15 is partially filled with intrinsic polysilicon whose upper portion is doped. A classic ONO (Oxide/Nitride/Oxide) layer 16 isolates the polysilicon fill 17 from the silicon substrate 11. Surrounding the top portion of the polysilicon fill 17, an SiO.sub.2 collar 18 is provided to increase the isolation between the doped polysilicon and the ONO layer 16 on the trench sidewall. As apparent from FIG. 1, the thickness of the Si.sub.3 N.sub.4 layer 12 is substantially thinner above the "array" region 13 than above the ".kerf/support/street" region 14, e.g. about 120 nm compared to about 150 nm (there has been a partial consumption of the Si.sub.3 N.sub.4 material forming passivation layer 12 mainly during collar formation). As such, structure 10 is a typical example of a part of a silicon wafer after a conventional deep isolation trench process used in the fabrication of 16 Mbits DRAM chips. Now, the shallow isolation trenches have to be delineated in the silicon substrate 11.
First, the structure 10 of FIG. 1 is coated with a layer 19 of a photosensitive material having a thickness of about 1.1 um. An adequate material is the photoresist labelled IP3250 commercially sold by TOKYO-OHKA, Tokyo, Japan. After deposition, the photoresist layer 19 is exposed, then baked and developed as standard to leave the patterned layer or mask still referenced 19 in FIG. 2. The purpose of this mask 19, referred to as the IT mask, is to define the locations of the shallow trenches at the surface of the silicon substrate 11. After the IT mask 19 has been defined, the process continues with the IT etch. The wafer is placed in an AME 5000, a MERIE plasma etcher manufactured by Applied Materials Inc., Santa Clara, Calif., USA with the following operating conditions:
NF.sub.3 . . . : 8 sccm PA1 N2 . . . : 65 sccm PA1 CHF.sub.3 . . . : 4 sccm PA1 Pressure . . . : 5.32 Pa (40 mTorr) PA1 Power . . . : 600 W PA1 Mag. field . . . : 0 Gauss PA1 Temp. cathode.: 20.degree. C. PA1 Time . . . : 275 s PA1 CHF.sub.3 . . . : 70 sccm PA1 NF.sub.3 . . . : 60 sccm PA1 Pressure . . . : 18.25 Pa (137 mTorr) PA1 Mag. field . . . : 0 Gauss PA1 RF Power . . . : 562 W PA1 Optical endpoint: Yes PA1 Overetch . . . : 12 s PA1 Sel. resist/TEOS: 1.5/1 (blanket) PA1 Uniformity . . . : &lt;2% PA1 CHF.sub.3 . . . : 80 sccm PA1 NF.sub.3 . . . : 50 sccm PA1 Pressure . . . : 30 Pa (220 mTorr) PA1 Mag field . . . : 20 Gauss PA1 RF Power . . . : 700 W PA1 Etch time . . . : 30 sec PA1 Sel. resist/TEOS: 1/1 (blanket) PA1 Uniformity . . . : &lt;2% PA1 CHF.sub.3 . . . : 95 sccm PA1 CO.sub.2 . . . : 40 sccm PA1 Pressure . . . : 20 Pa (150 mTorr) PA1 Mag. field . . . : 25 Gauss PA1 RF Power . . . : 900 W PA1 Optical endpoint: Yes PA1 Overetch . . . : No PA1 Sel. TEOS/resist: 6/1 (blanket) PA1 Uniformity . . . : &lt;3%
This etching mixture is not selective and thus attacks the different materials (polysilicon, SiO.sub.2, Si.sub.3 N.sub.4 and monocrystalline silicon) forming the exposed layers substantially at the same rate down to a deepness of about 675 nm. The IT mask 19 is then removed by ashing as standard. At this stage of the process, the structure 10 is shown in FIG. 3. Now turning to FIG. 3, two different sized shallow trenches, a narrow and a relatively wide, have been shown and are referenced by numerals 20A and 20B. In the "array" region 13, shallow trenches are required to nest the active devices of the memory elements and therefore must be as small as possible to increase integration density. On the contrary, in the ".kerf/support/street" area, the trenches are relatively wide for test device isolation. As apparent from FIG. 3, it remains isolated Si.sub.3 N.sub.4 pads still referenced 12.
The next step consists in the thermal growth of a sacrificial thin SiO.sub.2 layer on the portions of horizontal surfaces that are not protected by said Si.sub.3 N.sub.4 pads 12 and on the sidewalls of the shallow trenches 20A and B formed in the silicon substrate 11. This oxidation of silicon surfaces is performed in order to eliminate surface damages due to the preceding reactive ion etching (RIE) step (IT etch). At this stage of the process, as apparent from FIG. 4, the bottom and sidewalls of shallow trenches 20A and 20B are covered with a thin sacrificial SiO.sub.2 layer 21 having a thickness of about 22.5 nm (layer 21 will no longer be illustrated in the drawings).
Now, the shallow trenches 20A and 20B are filled with TEOS SiO.sub.2 material. To that end, a TEO.sub.2 S SiO layer 22 is conformally deposited onto the structure 10 with a thickness of about 845 nm to overfill the trench. An overfill of 175 nm is the target. This TEOS SiO.sub.2 layer 22 is generally formed by LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition) techniques using tetra ethyl ortho silicate (TEOS) and oxygen as standard. The resulting structure is shown in FIG. 5. A small depression 23A and a wide depression (or recess) 23B can be noticed above respective shallow trenches 20A and 20B. Another small depression referenced 23C is also illustrated in FIG. 5. Between depressions, the structure 10 surface presents typical mounts. At this stage of the fabrication, the structure 10 must be planarized and the initial thickness of the TEOS SiO.sub.2 layer 22 must be reduced to a given value determined by the product specifications.
The planarization basic step now takes place. In reality, it is comprised of two main processing steps: first forming a planarizing medium onto the surface of the structure 10 of FIG. 5, then planarizing the structure approximately down to the surface of the Si.sub.3 N.sub.4 pads 12 surface. In short, the main step of forming a planarizing medium will consist in the successive deposition of two photoresist layers and the planarization main step will be performed in two steps: first, an etch-back (referred to as the AB etch) of the structure which is performed in the same plasma etcher, then the resulting structure is chem-mech polished. In essence, the purpose of the AB etch is to reach the bottom of the recess 23B, while the purpose of the chem-mech polishing step is to have the final surface of the TEOS SiO.sub.2 layer 22 quite planar and at about -60 nm with respect to the Si.sub.3 N.sub.4 pads 12 surface.
Preferably, the main step of forming a planarizing medium is achieved in depositing two successive layers of photoresist. A first layer 24 (AB1) of a photoresist such as described in U.S. Pat. No. 5,273,856 assigned to IBM Corp. with a thickness of 830 nm is deposited onto the structure 10, then exposed, baked and developed as standard to leave a patterned layer referred to as AB1 mask still referenced 24. In essence, the aim of this mask 24 is to fill the wide depressions such as 23B and a determined number of small depressions such as 23A (but not 23C) as apparent from FIG. 5. This design is correlated to uniformity process problems to reduce the "silicon polish" related defects that will be discussed later on. Finally, the structure 10 is raised to a temperature sufficient (about 140.degree. C.) to cause the photoresist material of AB1 layer 24 to flow and completely fill the depressions.
Next, a second 830 nm thick layer 25 of the same photoresist material is applied over layer 24 and baked. After this second step, we can consider that the wafer surface is coarsely planar. In fact, some resist bubbles can occur and a slight relief topography does exist at locations where layers 24 and 25 are superposed. At this stage of the process, the structure 10 is shown in FIG. 7.
Now, the coarsely planarized surface of the FIG. 7 structure will be transferred to the TEOS SiO.sub.2 layer 22 to produce a thinner but substantially planar layer all over the silicon substrate 11. In reality, the AB etch step mentioned above is completed in three different sub-steps, to adjust the TEOS SiO.sub.2 layer 22 thickness whatever the pattern factor difference existing between the "array" and ".kerf/support/street" regions. The final objective is to etch the TEOS SiO.sub.2 layer 22 surface at the mount locations until the bottom of the wide depression 23B is attained. All these three sub-steps are achieved in the AME 5000 plasma etcher mentioned above, only the chemistries are different.
According to the first sub-step, the wafer is placed in the AME 5000 plasma etcher and the top resist AB2 layer 25 is etched until the surface of the TEOS SiO.sub.2 layer 22 (at mount locations) is reached. The operating conditions are:
By means of an adequate algorithm, an interferometric optical endpoint is used to detect the AB2 layer 25/TEOS SiO.sub.2 layer 22 interface. A fixed overetching is done after etch endpoint detection: about 40 nm of the TEOS SiO.sub.2 layer 22 at the mount locations and of the bottom AB1 resist layer 24 are removed during this overetch. The resulting structure is shown in FIG. 8.
Now the second etching sub-step is performed with the following operating conditions:
During this sub-step, the AB1 resist layer 24 and TEOS SiO.sub.2 layer 22 are supposed to be etched at the same rate. It is not completely true because of the pattern factor between "array" and ".kerf/support/street" regions. About 160 nm are etched for both resist layer 24 and TEOS SiO.sub.2 layer 22. At this stage of the fabrication, the structure is shown in FIG. 9. One may note the presence of small remains of the AB1 photoresist layer 24 at the location of the small depressions (e.g. 23A & 23C) and of a substantive remaining of the same at the location of the wide depression 23B. These remains will act as a mask for the subsequent processing step to be now described.
In the third and last sub-step, the TEOS SiO.sub.2 layer 22 is etched using the following operating conditions.
The resulting structure 10 at this stage of the process is shown in FIG. 10. This mixture has been selected so that during this sub-step, the TEOS SiO.sub.2 of layer 22 is etched faster than the material forming the AB1 photoresist layer 24 in order to be sure to protect the TEOS SiO.sub.2 material over the shallow isolation trenches 20A and 20B. As illustrated in FIG. 10, the etching has been conducted deeper in the "array" region 13 than desired (as mentioned above, the optimal level is the bottom of recess 23B). Due to different etch rates and anisotropic conditions, peak shaped TEOS SiO.sub.2 remains, usually called "fences", are left at the structure 10 surface. They are referenced 22' in FIG. 10.
At the end of the AB etch, the thickness of the remaining TEOS SiO.sub.2 layer 22 over Si.sub.3 N.sub.4 pads 12 is measured.
Finally, the remaining portions of the AB1 photoresist layer 24 are eliminated in a dedicated chamber of the AME 5000 plasma etcher. After photoresist stripping, the resulting structure 10 is shown in FIG. 11.
Now the step of chem-mech polishing is performed. During this step, the TEOS SiO.sub.2 layer 22 remaining over the Si.sub.3 N.sub.4 pads 12 is eliminated. The structure 10 is first chem-mech polished until the Si.sub.3 N.sub.4 pad surface is reached and the polishing is continued down to about 60 nm under Si.sub.3 N.sub.4 pads upper level. This step is achieved with commercially available polishing slurries. For example a suitable slurry is sold under commercial reference SC1 by CABOT-SPERCE, Eldorado Hills, Calif., USA. At this stage of the fabrication, the structure 10 is shown in FIG. 12.
The shallow trench formation process terminates by the steps of annealing the TEOS SiO.sub.2 layer 22 and the removal of the Si.sub.3 N.sub.4 pads 12. The anneal aims to densify the TEOS SiO.sub.2 material so that the final thickness is the thickness of the TEOS SiO.sub.2 layer 22 at the stage of FIG. 12 reduced by about 5%. At this stage of the fabrication, Si.sub.3 N.sub.4 pads 12 are quite necessary to protect the underlying monocrystalline silicon that would otherwise suffer. The Si.sub.3 N.sub.4 pads 12 stripping is performed by wet etching. As this wet process has a very high Si.sub.3 N.sub.4 /TEOS SiO.sub.2 selectivity, it is not capable to etch the Si.sub.3 N.sub.4 pads 12 in presence of a film of unpolished TEOS SiO.sub.2 material remaining thereon, even this film is very thin (e.g. 1.5 nm). Si.sub.3 N.sub.4 pads remains can be revealed only after this removal step.
The wafer road-map for the total AB etch sequence will be summarized by reference to FIG. 13. Now turning to FIG.13, there is schematically shown the AME 5000 plasma etcher referenced 26 comprised of four chambers 27A to 27D, a central load/unload module 28, a queueing station 29 coupled thereto and finally, vacuum locks that are referenced 30. FIG. 13 also shows the thickness measurement apparatus (e.g. a PROMETRIX) which bears numeral 31. Arrows illustrate the movements of the wafer within plasma etcher 26. As apparent from FIG. 13, only two reaction chambers are necessary. The three above mentioned sub-steps are conducted in chamber 27A while the remains of AB1 photoresist layer 24 are stripped in chamber 27B. The TEOS SiO.sub.2 thickness measurement is performed (above a Si.sub.3 N.sub.4 pad in the ".kerf/support/street" region) in the meantime in apparatus 31.
In the present fabrication process, the chem-mech polishing is a long and expensive processing step. Unfortunately, due to process monitoring difficulties: etch rate drifts as a function of the number of wafers to be polished, different etch rates between "array" and ".kerf/support/street" regions referred to as the "dishing effect" in the technical literature, the chem-mech polishing step is not performed in a single run but rather in two or three runs. Before the first run and between runs, all the wafers must be measured (this time, the TEOS SiO.sub.2 layer 22 thickness is measured at the center of a wide depression such as 23B) and process parameters adjusted. FIG. 14 shows the wafer road-map between the thickness measurement unit 32 (e.g. a PROMETRIX) and the chem-mech polisher 33 such as model 372M sold by WESTECH, Tempe, Ariz., USA. As known for those skilled in the art, the chem-mech polishing step has a very small process window since it is greatly dependent on all the previous processing steps, moreover it cannot heal any process variations. But, because the presence of fences 22' produced during AB etch, the chem-mech polishing step is really mandatory.
FIG. 15 illustrates the ideal structure that is sought at the end of the planarization main step described by reference to FIGS. 6 to 13. After the planarization main step, there is a "wrap-around" target of about -60 nm as clearly illustrated in the enlarged view of FIG. 15. Unfortunately, in spite of all the parameter adjustments mentioned above and outstanding cares, the wrap-around that is obtained can significantly vary between the first and the last wafer of a given lot and even between the "array" and ".kerf/support/street" regions of a same wafer.
Two types of problems appear when the above described planarization main step sequence (including the chem-mech polishing step which is a major contributor thereto) is used, they are usually referred to as "silicon polish" and "Si.sub.3 N.sub.4 pad residuals". These problems have different causes, including the thickness variations of the Si.sub.3 N.sub.4 layer 12 over the "array" and ".kerf/support/street" regions, the difficulty to properly control the chem-mech polishing step, and finally the effects due to different pattern factors.
If the chem-mech polishing is "too important", some Si.sub.3 N.sub.4 pads 12 will be completely removed and the silicon of substrate 11 is no longer protected during the anneal. As a final result, the gate oxide of IGFET's will be of poor quality. This case is illustrated in FIG. 16A where an arrow shows the exposed silicon surface. This directly results of the thickness variations in the Si.sub.3 N.sub.4 layer 12 as mentioned above.
On the contrary, if the chem-mech polishing step is "not long enough", in this case, some TEOS SiO.sub.2 material may remain over the Si.sub.3 N.sub.4 pads 12 and will act as a hard mask protecting film during the above mentioned Si.sub.3 N.sub.4 pad removal step thus preventing their complete removal. In this case, some Si.sub.3 N.sub.4 pads remain under the gate conductors (GC) as known for those skilled in the art which in turn, cause the IGFET's to be inoperative. This case is illustrated in FIG. 16B where an arrow shows an unremoved Si.sub.3 N.sub.4 pad.
In both cases, even if process adjustments made from measurements conducted in box 32 are appropriate, these defects cannot be satisfactorily corrected because chem-mech polishing is essentially a mechanical technique which cannot integrate all the possible variations or non-uniformities resulting from the previous processing steps. As a matter of fact, the process window of the chem-mech polishing step is very small and strongly depends on the product families. Zero yield at the final test can be expected for chips suffering of these defects. Finally, the above planarization step sequence does not allow the great reproducibility that is highly desired for the successful completion of processing steps to which the wafers will be subsequently submitted.